1. Field of the Invention
The disclosure relates in general to a conducting structure and method of fabricating the same, and more particularly to a three-dimensional conducting structure and method of fabricating the same.
2. Description of the Related Art
Generally speaking, system in package (SiP) includes the following technologies such as multi-chip module (MCM) technology, multi-hip package (MCP) technology, stack die technology, package on package (PoP) technology, package in package (PiP) and embedded substrate technology which embed the active/passive elements in the substrate. In terms of the appearance of the package structure, MCM is a two-dimensional package, and MCP, stack die, PoP, PiP are three-dimensional three-dimensional packages. The three-dimensional package which meets the requirements of miniaturization and high efficiency has become more popular in recent years.
On the part of interconnection technology, most of conventional two-dimensional or three-dimensional packages adopt wire bonding and a few adopt flip chip technology or a mixture of wire bonding and flip chip technology. Let a stack die be taken for example. The top chip communicates with other chips by way of wire bonding technology. As the number of stacked chips increases, the upper the chip, the longer the wire, and the overall efficiency of the package system is deteriorated. Also, in order to create a space for wire bonding, a divider is inserted between chips, further increasing the volume of the package.
In recent years, the through silicon via (TSV) technology, a new interconnection technology, is provided. Referring to FIGS. 1A˜1F, the process of a method of fabricating a TSV conductive structure is shown. Firstly, as indicated in FIG. 1A, a chip 10 is provided, and the front surface 10a of the chip has a thickness-enhanced solder pad 12. Then, as indicated in FIG. 1B, a first laser drilling process is applied by way of drilling a opening 14 from the back surface 10b of the chip until reaching the surface of the pad 12. As the chip is drilled from the back surface 10b, the problem of mal-alignment may easily occur. On the other hand, as the laser power is unstable and the selective ratio between the silicon (the chip material) and the metal (the pad material) is not high enough, the laser light may easily penetrate through the pad. Despite this problem can be resolved by thickening the pad 12, additional cost and time will be needed.
Referring to FIG. 1C, the opening 14 is filled with an insulator 16. Then, a second laser drilling process is applied as indicated in FIG. 1D, wherein an via 17 is formed by drilling within the insulator 16 until the surface of the pad 12 is reached. After that, as indicated in FIG. 1E, the via 17 is filled with a conducive material 18. Lastly, as indicated in FIG. 1F, the chip 10 and another chip 20 are bonded together, and the pad 12 of the chip 10 is electrically connected with the pad 22 of another chip 20 through the conductive material 18.
However, hole enlargement may easily occur during the second laser drilling process of forming the via 17 and result in current leakage. When laser drilling reaches the pad 12, the metallic material (that is, the pad 12) will reflect or deflect the laser light, and the insulator 16 neighboring the pad 12 will be burnt by the laser light. Consequently, the terminal end of the via 17 will become larger and the chip 10 may even be exposed. When the via 17 is re-filled with the conductive material 18, the conductive material 18 will contact the chip 10, making the conductive material 18 and the chip 10, which are supposed to be insulated, are electrically connected with each other and result in the problem of current leakage.